1. Field of the Invention
The present invention relates generally to methods for forming solder interconnection structures for directly interconnecting microelectronic substrates within microelectronic fabrications. More particularly, the present invention relates to methods for forming, with attenuated physical stress and strain, solder interconnection structures for directly interconnecting microelectronic substrates within microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
As a method for directly interconnecting microelectronic substrates of various varieties, it is common in the art of microelectronic fabrication to employ a solder interconnection method which employs a solder interconnection structure positioned interposed between a pair of opposing bond pads fabricated within a corresponding pair of microelectronic substrates desired to be directly interconnected, where upon thermal annealing and reflow of the solder interconnection structure positioned interposed between the pair of opposing bond pads there is formed a reflowed solder interconnection structure formed interposed between the pair of opposing bond pads, which reflowed solder interconnection structure electrically and mechanically directly interconnects the pair of microelectronic substrates. Commonly, although not exclusively, within the solder interconnection method: (1) the solder interconnection structure is formed as a truncated spherical shape formed flattened upon one of the bond pads formed upon one of the microelectronic substrates; and (2) the reflowed solder interconnection structure is formed as a barrel shape bridging between the pair of bond pads formed within the corresponding pair of microelectronic substrates.
While such solder interconnection methods and solder interconnection structures are quite common in the art of microelectronic fabrication, such solder interconnection methods and solder interconnection structures are nonetheless not entirely without problems in the art of microelectronic fabrication.
In particular, as microelectronic fabrication integration levels have increased and microelectronic fabrication functionality has also increased, so too has the absolute density and the areal density of solder interconnection structures employed within advanced microelectronic fabrications for directly interconnecting advanced microelectronic substrates within advanced microelectronic fabrications. While such increased absolute density and such increased areal density of solder interconnection structures is essential for providing advanced microelectronic fabrications with enhanced functionality, such increased absolute density of solder interconnection structures, and in particular such increased areal density of solder interconnection structures, is nonetheless problematic insofar as increased areal density of a conventional solder interconnection structure typically limits the height of the conventional solder interconnection structure since the conventional solder interconnection structure is, as noted above, typically formed with a truncated spherical shape formed upon a bond pad. Similarly, solder interconnection structures formed of limited height when employed within microelectronic fabrication for directly interconnecting microelectronic substrates within microelectronic fabrications are undesirable insofar as corresponding reflowed solder interconnection structures of limited height are generally insufficient to adequately deflect and dissipate thermally induced physical stress and strain encountered incident to fabrication and/or operation of a microelectronic fabrication comprised of a pair of reflowed solder interconnection structure interconnected microelectronic substrates.
It is thus desirable within the art of microelectronic fabrication to fabricate solder interconnection structures for use when directly interconnecting microelectronic substrates employed within microelectronic fabrications in a fashion such as to attenuate thermally induced physical stress and strain within corresponding thermally reflowed solder interconnection structures with respect to microelectronic substrates which are directly interconnected with those thermally reflowed solder interconnection structures.
It is similarly towards the foregoing object that the present invention is directed.
Various methods and materials have been disclosed within the art of microelectronic fabrication for forming, with desirable properties, interconnection structures for directly interconnecting microelectronic substrates within microelectronic fabrications.
For example, Michelle M. Hou, in "Super CSP: The Wafer Level Package," Semiconductor Packaging Symposium, Session V: Chipscale Packaging, SEMI (1998), pp. F-1 to F-10, discloses a cost effective solder interconnection method and a resulting solder interconnection structure interconnected microelectronic fabrication comprising a semiconductor substrate directly interconnected with an additional microelectronic substrate. The solder interconnection method employs forming a series of solder interconnection layers upon a corresponding series of bond pads formed over multiple integrated circuit die within a single semiconductor substrate, wherein the single semiconductor substrate is encapsulated with a resin prior to parting the semiconductor substrate to form the integrated circuit die having formed thereover the solder interconnection layers formed upon the bond pads.
In addition, Agarwala et al., in U.S. Pat. No. 5,130,779, disclose: (1) a solder interconnection structure with an enhanced aspect ratio for use within a microelectronic fabrication for directly interconnecting, with attenuated physical stress and strain, a pair of microelectronic substrates within the microelectronic fabrication; and (2) a method for forming the solder interconnection structure with the enhanced aspect ratio for use within the microelectronic fabrication for directly interconnecting, with attenuated physical stress and strain, the pair of microelectronic substrates within the microelectronic fabrication. The solder interconnection method employs forming upon at least one solder interconnection layer employed within the solder interconnection structure, prior to thermal reflow of the solder interconnection layer: (1) a capping or encapsulant metal layer, or in the alternative; (2) a sidewall spacer layer, such that upon thermal reflow of the at least one solder interconnection layer the at least one solder interconnection layer is not susceptible to thermal reflow induced collapse.
Further, Petroz, in U.S. Pat. No. 5,225,634, discloses a hybrid circuit microelectronic fabrication comprising a pair of microelectronic substrates directly interconnected with a series electrical interconnection layers, wherein the hybrid circuit microelectronic fabrication is fabricated absent thermally induced physical stress or strain of the pair of microelectronic substrates with respect to the series of electrical interconnection layers. The hybrid circuit microelectronic fabrication realizes the foregoing object by employing when fabricating the hybrid circuit microelectronic fabrication: (1) electrical interconnection layers which are formed as spheres which are non-adherent to pairs of counter opposed bond pads upon which they are landed within the corresponding pair of microelectronic substrates within the hybrid circuit microelectronic fabrication; and (2) bond pads which are formed as tracks upon which the spherical electrical interconnection layers may freely rotate.
Finally, Tsukamoto, in U.S. Pat. No. 5,640,052, discloses a solder interconnection structure for use when directly interconnecting a pair of microelectronic substrates within a microelectronic fabrication, where the solder interconnection structure provides for attenuated thermally induced physical stress and strain of the pair of microelectronic substrate with respect to the solder interconnection structure when directly interconnecting the pair of microelectronic substrates within the microelectronic fabrication while employing the solder interconnection structure. To realize the foregoing object, the solder interconnection structure employs a metal core layer having formed thereupon a solder interconnection layer which bridges to a pair of bond pads formed within the pair of microelectronic substrates, where the solder interconnection layer which bridges to the pair of bond pads formed within the pair of microelectronic substrates is formed with an hourglass shape.
Desirable in the art of microelectronic fabrication are additional methods and materials which may be employed for forming within the art of microelectronic fabrication solder interconnection structures for directly interconnecting a pair of microelectronic substrates within a microelectronic fabrication, where upon thermal reflow to form a reflowed solder interconnection structure, the reflowed solder interconnection structure is formed with attenuated thermally induced physically stress and strain with respect to the pair of microelectronic substrates.
It is towards the foregoing object that the present invention is directed.